How To Address Registers In Psoc 5lp

Nosotros conclude our ballsy with the translation of Cypress proprietary documentation about UDB. The latest effect - about addressing UDB - is in front of you.

The general content of the cycle "UDB. What is information technology?"
Part 1. Introduction. Pld.
Part 2. Datapath.
Office 3. Datapath FIFO.
Part 4. Datapath ALU.
Function 5. Datapath. Useful little things.
Part 6. Management and status module.
Function 7. Timing and reset control module.
Part viii. UDB addressing. (Current article)

21.iii.five UDB Addressing

The UDB pair has 3 unique address spaces:

8-bit working registers - a motorcoach controller that has access to merely 8 bits of data per passenger vehicle cycle tin employ this accost space to read or write any UDB working registers. These include the registers with which the CPU and DMA interact during normal operation.
16-bit work registers - A 16-bit omnibus controller, such equally a DMA or PSoC 5LP Cortex-M3, tin access 16 bits in one charabanc bike to enable data transfer to functions that crave sixteen bits or more. Despite the fact that this address space is not tied to the surface area to which the 8-bit space is tied, information technology has access to the same registers, only to a pair at a time.
8- or xvi-fleck configuration registers - these registers configure UDB to execute a part. After configuration, the registers are commonly gear up to a static state during UDB operation. These registers retain their country subsequently sleep way.

Translator's Note
Everything is somehow complicated. In my opinion, for the beginning two points it is easier to introduce the concept of addressing methods with different bit depths of the working register. Through 8-scrap and through sixteen-bit working registers respectively. If you are confused when reading these paragraphs, attempt to consider the text in this way. Different windows in the address space of the CPU, providing addressing of the aforementioned through the working registers of different bits. That's all.

21.3.5.1 Working Register Address Space

Piece of work registers are used during normal operation and include batteries, data registers, FIFOs, command and condition registers, a mask superimposing register, and an auxiliary control register.

Figure 21-43 shows a register map of one UDB.

On the right in Effigy 21-43 is a 16-bit address that is ever even. In this example, the UDB number has a dimension of 5 bits, non four, due to the fifty-fifty location of the addresses. The high 4 bits still set the register number.

Figure 21-43. Working registers UDB.

8-bit working register access
In this mode, access to all UDB registers is via addresses aligned on the byte boundary. In access fashion for 8-bit registers, as shown in Figure 21-44, all information bytes written to UDB are aligned with the depression byte of the 16-fleck UDB bus.

In this mode, access at whatsoever fourth dimension can only be accessed to one byte.

Figure 21-44. Access to 8-chip working register.

sixteen-Bit Working Register Accost Space
A sixteen-bit address space designed for efficient DMA access and providing programmatic CPU access in processors that back up information technology, such equally the Cortex-M3 in PSoC 5LP. There are 2 modes of access to 16-chip registers: the default mode and the concatenation mode. Every bit shown in Effigy 21-45, in default mode it accesses the specified register in UDB 'i' through the low byte and to the same register in UDB 'i + one' through the loftier byte. This makes processing 16-bit data efficient in neighboring UDBs (in order of addresses) configured equally 16-chip functions.

Effigy 21-45. Access to 16-scrap working registers in default mode.

In concatenation fashion, the registers of one UDB are combined to grade sixteen-bit registers, as shown in Figure 21-46. In this mode, the 16-bit information bus of the UDB assortment must access a pair of registers in the UDB in the format shown in the figure. For instance, when accessing the register A0, access to A0 through the low byte and to A1 through the high byte volition actually occur.

Figure 21-46. Access to a 16-bit working register in concatenation way.

The use of DMA is express past the capacity of the 16-bit working register. It is non enough when working with functions greater than 16 bits. This is caused past address overlays, as shown in
table 21-25.

Tables 21-25. Optimized address space for 16-bit UDB functions.

When the DMA transmits 16 bits to address 0, the low and high bytes are written to UDB0 and UDB1, respectively. In the next 16-bit DMA manual to accost 2, the value in UDB1 is overwritten by the low byte of this transmission.

To prevent problems associated with such memory arrangement, it is recommended for functions whose bit depth is more than 16 $.25 to commencement the DMA process for an area with 8-scrap working registers.

21.iii.5.ii Configuration Annals Accost Space

Configuration is done at the UDB pair level. A UDB pair consists of 2 UDBs and an associated tracer channel, as shown in Effigy 21-47.

Figure 21-47. Address scheme for configuring a UDB pair.

21.iii.5.three UDB Configuration Accost Space

Figure 21-48 shows the address configuration diagram of a specific UDB. As yous can meet, this configuration space is duplicated on both UDBs in pairs. In total, 128 bytes (7 bit addresses) are reserved for each UDB configuration, which are divided into 16-bit segments. It is worth noting that xvi-flake admission to odd borders is not supported. Reading always returns 16 bits in the configuration space, and unnecessary bytes can be ignored.

Figure 21-48. The address space of the UDB configuration.

21.3.5.four Routing Configuration Address Space

The UDB trace configuration consists of embedded RAM bits to control the status of gateway switches, sectionalization, and input / output buffers.

21.3.vi System Motorbus Access Coherency

UDB registers take dual admission way:

access to the system bus, in which the CPU or DMA reads or writes to the UDB register;
UDB internal access, in which the UDB function updates or uses the contents of the register

21.3.6.i Simultaneous System Charabanc Access

The table below contains a list of possible concurrent access events and the required behavior.

Table 21-26. Simultaneous admission to the system coach.

a. Ax registers tin be safely read using the FIFO software capture role.
b. In Dx registers, FIFOs tin just exist dynamically written. In this mode, straight reading of Dx registers is not available.
c. The CNT register can only be read safely when information technology is disabled. An alternative for dynamically reading the CNT value is tracing the output to the SC register (in transparent mode).
d. MC register bits can be traced to the condition register inputs (in transparent fashion) for condom reading.

21.iii.six.2 Coherent Accumulator Access (Diminutive Reads and Writes)

UDB batteries are the main goal of information processing. Therefore, reading these registers directly during normal operation gives an undefined result, every bit shown in the table above. However, at that place is built-in support for atomic readings in the form of program capture implemented on blocks connected in a chain. In such a usage model, reading the final significant bombardment transfers information from all the blocks connected in the chain to the associated FIFOs. Atomic recording in FIFO can be implemented programmatically. Individual write operations can exist performed at the FIFO input, and then the FIFO status bespeak to which the concluding recording was made tin can be forwarded to all linked blocks, while the FIFO data will be transferred to the Dx or Ax registers.

Afterword from the translator

This translation cycle was made as a response to the commentary on the article , where it was proposed offset to briefly describe what UDB is. At present information technology is clear that for a brief respond it would be necessary to quote at least half of the materials presented hither, otherwise the answer would still be incomplete. Only now all the materials are translated and compiled. Mission achieved.

While the work was going on, we also drew attention to some other interesting PSoC block, which is poorly known to anyone, only is fraught with tremendous power. This is DFB, Digital Filter Block. True, it'due south scary to rush into the translation. From the translation about UDB it is clear that one documentation is not enough, oh, practice is needed. The trouble is that in that location are few ready-fabricated examples on UDB, but they are. Information technology has non yet been possible to find something worthwhile from the examples on DFB (Cypress itself made a digital filter in the form of a black box, it works, but information technology'south not articulate how). Translation without examples volition not make sense. Therefore, taking this opportunity, we draw the attention of readers to this block. Possibly someone in the comments volition provide links to good examples. If we manage to deal with this block, it will be possible to make a cycle of translations and applied articles on it. In the concurrently, that's all.